Texas Instruments MSP430x1xx User Manual page 190

DMA Bit 6 DMA source byte. This bit selects the source as a byte or word.
SRCBYTE
0
1
DMA Bit 5 DMA level. This bit selects between edge-sensitive and level-sensitive
LEVEL
triggers.
0
1
DMAEN Bit 4 DMA enable
0
1
DMAIFG Bit 3 DMA interrupt flag
0
1
DMAIE Bit 2 DMA interrupt enable
0
1
DMA Bit 1 DMA Abort. This bit indicates if a DMA transfer was interrupt by an NMI.
ABORT
0
1
DMAREQ Bit 0 DMA request. Software-controlled DMA start. DMAREQ is reset
automatically.
0
1
DMAxSA, DMA Source Address Register
15 14
rw rw
7 6
rw rw
DMAxSAx Bits DMA source address. The source address register points to the DMA source
15−0 address for single transfers or the first source address for block transfers. The
source address register remains unchanged during block and burst-block
transfers.
8-22
Word
Byte
Edge sensitive (rising edge)
Level sensitive (high level)
Disabled
Enabled
No interrupt pending
Interrupt pending
Disabled
Enabled
DMA transfer not interrupted
DMA transfer was interrupted by NMI
No DMA start
Start DMA
13 12 11
DMAxSAx
rw rw rw
5 4 3
DMAxSAx
rw rw rw
10 9 8
rw rw rw
2 1 0
rw rw rw