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Figure 15−8. Master Transmitter Mode
IDLE
I2CSTT=1
4 x I2CPSC
Generate START
I2CBUSY Is Set
8 x I2CPSC
I2CBB Is Set
I2CSTT Is Cleared
XA=0
8 x SCL
Send Slave
Address Bits 6−0
with R/W=0
1
No Ack
Ack
Repeat Mode?
I2CRM=1
Yes
STOP State?
Yes
No
2
Ack, and
I2CWORD=0
*When I2RM=1, I2CSTP must be set before the last I2CDR value
3
is written. Othwerwise, correct STOP generation will not occur.
XA=1
8 x SCL
Send Slave Address
Bits 9−8 Extended
with R/W = 0
8 x SCL
Send Slave Address
Bits 7−0
Ack
I2CRM=0
I2CNDAT
Number Of Bytes
Sent?
No
No
I2CDR Empty
I2CDR Loaded?*
I2CDR Written
8 x SCL
Send I2CDR
Low Byte
No Ack
Ack
8 x SCL
Send I2CDR
High Byte
No Ack
Ack
New START?
USART Peripheral Interface, I
2
I
C Module Operation
1
No ACK
NACKIFG Is Set
IDLE
I2CBUSY Is Cleared
Yes
STOP State?
Yes I2CSTP=1
10 x I2CPSC
Generate STOP
No
8 x I2CPSC
I2CBB Is Cleared
8 x I2CPSC
I2CSTP, I2CMST
Are Cleared
1
IDLE
I2CBUSY Is Cleared
New START?
3
Yes
2
C Mode
2
No
15-9
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