Texas Instruments MSP430x1xx User Manual page 76

Instruction Set
* EINT Enable (general) interrupts
Syntax EINT
1 → GIE
Operation
or
(0008h .OR. SR −> SR / .src .OR. dst −> dst)
Emulation BIS
Description All interrupts are enabled.
The constant #08h and the status register SR are logically ORed. The result
is placed into the SR.
Status Bits Status bits are not affected.
Mode Bits GIE is set. OSCOFF and CPUOFF are not affected.
Example The general interrupt enable (GIE) bit in the status register is set.
; Interrupt routine of ports P1.2 to P1.7
; P1IN is the address of the register where all port bits are read. P1IFG is the address of
; the register where all interrupt events are latched.
;
PUSH.B
BIC.B
EINT
BIT
JEQ
......
MaskOK BIC
......
INCD
RETI
Note: Enable Interrupt
The instruction following the enable interrupt instruction (EINT) is always
executed, even if an interrupt service request is pending when the interrupts
are enable.
RISC 16−Bit CPU
3-40
#8,SR
&P1IN
@SP,&P1IFG ; Reset only accepted flags
; Preset port 1 interrupt flags stored on stack
; other interrupts are allowed
#Mask,@SP
MaskOK ; Flags are present identically to mask: jump
#Mask,@SP
SP ; Housekeeping: inverse to PUSH instruction
; at the start of interrupt subroutine. Corrects
; the stack pointer.