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Figure 8−4. DMA Block Transfer State Diagram
DMAEN = 0
DMAEN = 0
DMAREQ = 0
T_Size → DMAxSZ
[DMADTx = 1
AND DMAxSZ = 0]
OR
DMAEN = 0
DMAABORT = 1
DMAABORT=0
2 x MCLK
[ENNMI = 1
AND NMI event]
OR
[DMALEVEL = 1
AND Trigger = 0]
Reset
DMAEN = 0
DMAEN = 1
DMAxSZ → T_Size
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
Idle
Wait for Trigger
[+Trigger AND DMALEVEL = 0 ]
OR
[Trigger=1 AND DMALEVEL=1]
Hold CPU,
Transfer one word/byte
DMAxSZ > 0
Decrement DMAxSZ
Modify T_SourceAdd
Modify T_DestAdd
DMAREQ = 0
T_Size → DMAxSZ
DMAxSA → T_SourceAdd
DMAxDA → T_DestAdd
DMADTx = 5
AND DMAxSZ = 0
AND DMAEN = 1
8-9
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