Texas Instruments MSP430x1xx User Manual page 379

ADC12CTL0, ADC12 Control Register 0
15 14
SHT1x
rw−(0) rw−(0)
7 6
MSC REF2_5V
rw−(0) rw−(0)
Modifiable only when ENC = 0
SHT1x Bits Sample-and-hold time. These bits define the number of ADC12CLK cycles in
15-12 the sampling period for registers ADC12MEM8 to ADC12MEM15.
SHT0x Bits Sample-and-hold time. These bits define the number of ADC12CLK cycles in
11-8 the sampling period for registers ADC12MEM0 to ADC12MEM7.
SHTx Bits
13 12
rw−(0) rw−(0) rw−(0)
5 4
REFON ADC12ON ADC12OVIE
rw−(0) rw−(0) rw−(0)
ADC12CLK cycles
0000 4
0001 8
0010 16
0011 32
0100 64
0101 96
0110 128
0111 192
1000 256
1001 384
1010 512
1011 768
1100 1024
1101 1024
1110 1024
1111 1024
11 10 9
SHT0x
rw−(0) rw−(0)
3 2 1
ADC12
ENC
TOVIE
rw−(0) rw−(0)
ADC12 Registers
8
rw−(0)
0
ADC12SC
rw−(0)
ADC12 17-21