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Single Transfer
In single transfer mode, each byte/word transfer requires a separate trigger.
The single transfer state diagram is shown in Figure 8−3.
The DMAxSZ register is used to define the number of transfers to be made.
The DMADSTINCRx and DMASRCINCRx bits select if the destination
address and the source address are incremented or decremented after each
transfer. If DMAxSZ = 0, no transfers occur.
The DMAxSA, DMAxDA, and DMAxSZ registers are copied into temporary
registers. The temporary values of DMAxSA and DMAxDA are incremented
or decremented after each transfer. The DMAxSZ register is decremented
after each transfer. When the DMAxSZ register decrements to zero it is
reloaded from its temporary register and the corresponding DMAIFG flag is
set. When DMADTx = 0, the DMAEN bit is cleared automatically when
DMAxSZ decrements to zero and must be set again for another transfer to
occur.
In repeated single transfer mode, the DMA controller remains enabled with
DMAEN = 1, and a transfer occurs every time a trigger occurs.
8-6
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