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Figure 14−1. USART Block Diagram: SPI Mode
SWRST USPIEx* URXEIE URXWIE
FE
PE
OE
BRK
Receive Status
RXERR
RXWAKE
SSEL1 SSEL0
SP
UCLKI
00
ACLK
01
SMCLK
10
SMCLK
11
SP
WUT
TXWAKE
UTXIFGx*
SWRST USPIEx* TXEPT
* Refer to the device-specific datasheet for SFR locations
URXIFGx*
Receive Control
Receiver Buffer UxRXBUF
Receiver Shift Register
CHAR
PEV
PENA
UCLKS
Baud−Rate Generator
Prescaler/Divider UxBRx
Modulator UxMCTL
CHAR
PEV
PENA
Transmit Shift Register
Transmit Buffer UxTXBUF
Transmit Control
STC
UCLKI
USART Peripheral Interface, SPI Mode
USART Introduction: SPI Mode
LISTEN
MM
1
0
1
1
0
0
1
0
1
1
0
0
SYNC CKPH CKPL
Clock Phase and Polarity
SYNC= 1
SYNC
SOMI
URXD
STE
UTXD
SIMO
UCLK
14-3
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