Texas Instruments MSP430x1xx User Manual page 188

DMACTL1, DMA Control Register 1
15 14
0 0
r0 r0
7 6
0 0
r0 r0
Reserved Bits Reserved. Read only. Always read as 0.
15−3
DMA Bit 2 DMA on fetch
ONFETCH
0
1
ROUND
Bit 1 Round robin. This bit enables the round-robin DMA channel priorities.
ROBIN
0
1
ENNMI Bit 0 Enable NMI. This bit enables the interruption of a DMA transfer by an NMI
interrupt. When an NMI interrupts a DMA transfer, the current transfer is
completed normally, further transfers are stopped, and DMAABORT is set.
0
1
8-20
13 12 11
0 0 0
r0 r0 r0
5 4 3
0 0 0
r0 r0 r0
The DMA transfer occurs immediately
The DMA transfer occurs on next instruction fetch after the trigger
DMA channel priority is DMA0 − DMA1 − DMA2
DMA channel priority changes with each transfer
NMI interrupt does not interrupt DMA transfer
NMI interrupt interrupts a DMA transfer
10 9
0 0
r0 r0
2 1
DMA ROUND
ENNMI
ONFETCH ROBIN
rw−(0) rw−(0)
8
0
r0
0
rw−(0)