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DAC12_xCTL, DAC12 Control Register
15
14
Reserved
DAC12SREFx
rw−(0)
rw−(0)
7
6
DAC12AMPx
rw−(0)
rw−(0)
Modifiable only when DAC12ENC = 0
Reserved
Bit 15
Reserved
DAC12
Bits
DAC12 select reference voltage
SREFx
14-13
00
01
10
11
DAC12
Bit 12
DAC12 resolution select
RES
0
1
DAC12
Bits
DAC12 load select. Selects the load trigger for the DAC12 latch. DAC12ENC
LSELx
11-10
must be set for the DAC to update, except when DAC12LSELx = 0.
00
01
10
11
DAC12
Bit 9
DAC12 calibration on. This bit initiates the DAC12 offset calibration sequence
CALON
and is automatically reset when the calibration completes.
0
1
DAC12IR
Bit 8
DAC12 input range. This bit sets the reference input and voltage output range.
0
1
13
12
11
DAC12RES
rw−(0)
rw−(0)
rw−(0)
5
4
DAC12DF
DAC12IE
rw−(0)
rw−(0)
rw−(0)
V
REF+
V
REF+
Ve
REF+
Ve
REF+
12-bit resolution
8-bit resolution
DAC12 latch loads when DAC12_xDAT written (DAC12ENC is ignored)
DAC12 latch loads when DAC12_xDAT written, or, when grouped,
when all DAC12_xDAT registers in the group have been written.
Rising edge of Timer_A.OUT1 (TA1)
Rising edge of Timer_B.OUT2 (TB2)
Calibration is not active
Initiate calibration/calibration in progress
DAC12 full-scale output = 3x reference voltage
DAC12 full-scale output = 1x reference voltage
10
9
DAC12
DAC12LSELx
CALON
rw−(0)
rw−(0)
3
2
1
DAC12IFG
DAC12ENC
rw−(0)
rw−(0)
DAC12 Registers
8
DAC12IR
rw−(0)
0
DAC12
GRP
rw−(0)
DAC12
19-11
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