Table of Contents
Advertisement
ADC10 Registers
ADC10DTC0, Data Transfer Control Register 0
7
6
Reserved
r0
r0
Reserved
Bits
Reserved. Always read as 0.
7-4
ADC10TB
Bit 3
ADC10 two-block mode.
0
1
ADC10CT
Bit 2
ADC10 continuous transfer.
0
1
ADC10B1
Bit 1
ADC10 block one. This bit indicates for two-block mode which block is filled
with ADC10 conversion results. ADC10B1 is valid only after ADC10IFG has
been set the first time during DTC operation. ADC10TB must also be set
0
1
ADC10
Bit 0
This bit should normally be reset.
FETCH
18-30
ADC10
5
4
3
ADC10TB
r0
r0
rw−(0)
One-block transfer mode
Two-block transfer mode
Data transfer stops when one block (one-block mode) or two blocks
(two-block mode) have completed.
Data is transferred continuously. DTC operation is stopped only if
ADC10CT cleared, or ADC10SA is written to.
Block 2 is filled
Block 1 is filled
2
1
ADC10
ADC10CT
ADC10B1
FETCH
rw−(0)
rw−(0)
rw−(0)
0
Advertisement
Table of Contents
