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Figure 15−1. USART Block Diagram: I
I2CSSELx
I2CBUSY
No clock
00
ACLK
01
I2CIN
SMCLK
10
SMCLK
11
I2CRXOVR
I2CSBD
I2CWORD
XA
2
C Mode
I2C Clock Generator
I2CPSC
I2CSCLL
I2CSCLH
Receive Shift Register
I2CSTP
I2CSTT
Transmit Shift Register
I2CTXUDF
I2CDRW
I2COA
I2CSA
USART Peripheral Interface, I
2
I
C Module Introduction
I2CEN
I2CSCLLOW
I2CCLK
1
MST
I2CTRX
LISTEN
0
1
I2CSTB
I2CNDATx
2
C Mode
SYNC = 1
I2C = 1
SCL
R/W
0
SDA
1
I2CRM
15-3
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