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USART Operation: UART Mode
Automatic Error Detection
Glitch suppression prevents the USART from being accidentally started. Any
low-level on URXDx shorter than the deglitch time t
will be ignored. See the device-specific datasheet for parameters.
When a low period on URXDx exceeds t
bit. If the majority vote fails to detect a valid start bit the USART halts character
reception and waits for the next low period on URXDx. The majority vote is also
used for each bit in a character to prevent bit errors.
The USART module automatically detects framing errors, parity errors,
overrun errors, and break conditions when receiving characters. The bits FE,
PE, OE, and BRK are set when their respective condition is detected. When
any of these error flags are set, RXERR is also set. The error conditions are
described in Table 13−1.
Table 13−1.Receive Error Conditions
Framing error
Parity error
Receive overrun error
Break condition
When URXEIE = 0 and a framing error, parity error, or break condition is
detected, no character is received into UxRXBUF. When URXEIE = 1,
characters are received into UxRXBUF and any applicable error bit is set.
When any of the FE, PE, OE, BRK, or RXERR bits is set, the bit remains set
until user software resets it or UxRXBUF is read.
13-8
USART Peripheral Interface, UART Mode
Error Condition
A framing error occurs when a low stop bit is
detected. When two stop bits are used, only the first
stop bit is checked for framing error. When a
framing error is detected, the FE bit is set.
A parity error is a mismatch between the number of
1s in a character and the value of the parity bit.
When an address bit is included in the character, it
is included in the parity calculation. When a parity
error is detected, the PE bit is set.
An overrun error occurs when a character is loaded
into UxRXBUF before the prior character has been
read. When an overrun occurs, the OE bit is set.
A break condition is a period of 10 or more low bits
received on URXDx after a missing stop bit. When a
break condition is detected, the BRK bit is set. A
break condition can also set the interrupt flag
URXIFGx.
(approximately 300 ns)
τ
a majority vote is taken for the start
τ
Description
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