Table of Contents
Advertisement
DMAxCTL, DMA Channel x Control Register
15
14
Reserved
rw−(0)
rw−(0)
7
6
DMA
DMA
DSTBYTE
SRCBYTE
rw−(0)
rw−(0)
Reserved
Bit 15
Reserved
DMADTx
Bits
DMA Transfer mode.
14−12
000 Single transfer
001 Block transfer
010 Burst-block transfer
011 Burst-block transfer
100 Repeated single transfer
101 Repeated block transfer
110 Repeated burst-block transfer
111 Repeated burst-block transfer
DMA
Bits
DMA destination increment. This bit selects automatic incrementing or
DSTINCRx
11−10
decrementing of the destination address after each byte or word transfer.
When DMADSTBYTE=1, the destination address increments/decrements by
one.
increments/decrements by two. The DMAxDA is copied into a temporary
register and the temporary register is incremented or decremented. DMAxDA
is not incremented or decremented.
00
01
10
11
DMA
Bits
DMA source increment. This bit selects automatic incrementing or
SRCINCRx
9−8
decrementing of the source address for each byte or word transfer. When
DMASRCBYTE=1, the source address increments/decrements by one.
When DMASRCBYTE=0, the source address increments/decrements by
two. The DMAxSA is copied into a temporary register and the temporary
register is incremented or decremented. DMAxSA is not incremented or
decremented.
00
01
10
11
DMA
Bit 7
DMA destination byte. This bit selects the destination as a byte or word.
DSTBYTE
0
1
13
12
DMADTx
rw−(0)
rw−(0)
5
4
DMALEVEL
DMAEN
DMAIFG
rw−(0)
rw−(0)
When
DMADSTBYTE=0,
Destination address is unchanged
Destination address is unchanged
Destination address is decremented
Destination address is incremented
Source address is unchanged
Source address is unchanged
Source address is decremented
Source address is incremented
Word
Byte
11
10
DMADSTINCRx
rw−(0)
rw−(0)
rw−(0)
3
2
DMA
DMAIE
ABORT
rw−(0)
rw−(0)
rw−(0)
the
destination
9
8
DMASRCINCRx
rw−(0)
1
0
DMAREQ
rw−(0)
address
8-21
Advertisement
Table of Contents
