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ADC12CTL1, ADC12 Control Register 1
15
14
CSTARTADDx
rw−(0)
rw−(0)
7
6
ADC12DIVx
rw−(0)
rw−(0)
Modifiable only when ENC = 0
CSTART
Bits
Conversion
ADDx
15-12
conversion-memory register is used for a single conversion or for the first
conversion in a sequence. The value of CSTARTADDx is 0 to 0Fh,
corresponding to ADC12MEM0 to ADC12MEM15.
SHSx
Bits
Sample-and-hold source select
11-10
00
01
10
11
SHP
Bit 9
Sample-and-hold pulse-mode select. This bit selects the source of the
sampling signal (SAMPCON) to be either the output of the sampling timer or
the sample-input signal directly.
0
1
ISSH
Bit 8
Invert signal sample-and-hold
0
1
ADC12DIVx
Bits
ADC12 clock divider
7-5
000 /1
001 /2
010 /3
011 /4
100 /5
101 /6
110 /7
111 /8
13
12
11
rw−(0)
rw−(0)
rw−(0)
5
4
ADC12SSELx
rw−(0)
rw−(0)
rw−(0)
start
address.
ADC12SC bit
Timer_A.OUT1
Timer_B.OUT0
Timer_B.OUT1
SAMPCON signal is sourced from the sample-input signal.
SAMPCON signal is sourced from the sampling timer.
The sample-input signal is not inverted.
The sample-input signal is inverted.
10
9
SHSx
SHP
rw−(0)
rw−(0)
3
2
1
CONSEQx
rw−(0)
rw−(0)
These
bits
select
ADC12 Registers
8
ISSH
rw−(0)
0
ADC12
BUSY
r−(0)
which
ADC12
ADC12
17-23
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