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2
I
C Module Operation
2
15.2.2 I
C Serial Data
One clock pulse is generated by the master device for each data bit
transferred. The I
significant bit first as shown in Figure 15−3.
The first byte after a START condition consists of a 7-bit slave address and the
R/W bit. When R/W = 0, the master transmits data to a slave. When R/W = 1,
the master receives data from a slave. The ACK bit is sent from the receiver
after each byte on the 9th SCL clock.
2
Figure 15−3. I
C Module Data Transfer
SDA
MSB
SCL
1
2
START
Condition (S)
START and STOP conditions are generated by the master and are shown in
Figure 15−3. A START condition is a high-to-low transition on the SDA line
while SCL is high. A STOP condition is a low-to-high transition on the SDA line
while SCL is high. The busy bit, I2CBB, is set after a START and cleared after
a STOP.
Data on SDA must be stable during the high period of SCL as shown in
Figure 15−4. The high and low state of SDA can only change when SCL is low,
otherwise START or STOP conditions will be generated.
Figure 15−4. Bit Transfer on the I
SDA
SCL
15-6
USART Peripheral Interface, I
2
C module operates with byte data. Data is transferred most
Acknowledgement
Signal From Receiver
7
8
9
1
R/W
ACK
2
C Bus
Data Line
Stable Data
2
C Mode
Acknowledgement
Signal From Receiver
2
8
9
ACK
Change of Data Allowed
STOP
Condition (P)
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