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USART Registers: UART Mode
UxCTL, USART Control Register
7
6
PENA
PEV
rw−0
rw−0
PENA
Bit 7
Parity enable
0
1
PEV
Bit 6
Parity select. PEV is not used when parity is disabled.
0
1
SPB
Bit 5
Stop bit select. Number of stop bits transmitted. The receiver always
checks for one stop bit.
0
1
CHAR
Bit 4
Character length. Selects 7-bit or 8-bit character length.
0
1
LISTEN
Bit 3
Listen enable. The LISTEN bit selects loopback mode.
0
1
SYNC
Bit 2
Synchronous mode enable
0
1
MM
Bit 1
Multiprocessor mode select
0
1
SWRST
Bit 0
Software reset enable
0
1
13-22
USART Peripheral Interface, UART Mode
5
4
3
SPB
CHAR
LISTEN
rw−0
rw−0
rw−0
Parity disabled.
Parity enabled. Parity bit is generated (UTXDx) and expected
(URXDx). In address-bit multiprocessor mode, the address bit is
included in the parity calculation.
Odd parity
Even parity
One stop bit
Two stop bits
7-bit data
8-bit data
Disabled
Enabled. UTXDx is internally fed back to the receiver.
UART mode
SPI Mode
Idle-line multiprocessor protocol
Address-bit multiprocessor protocol
Disabled. USART reset released for operation
Enabled. USART logic held in reset state
2
1
SYNC
MM
SWRST
rw−0
rw−0
rw−1
0
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