Texas Instruments MSP430x1xx User Manual page 284

USART Registers: UART Mode
UxRCTL, USART Receive Control Register
7 6
FE PE
rw−0 rw−0
FE
Bit 7 Framing error flag
0
1
PE Bit 6 Parity error flag. When PENA = 0, PE is read as 0.
0
1
OE Bit 5 Overrun error flag. This bit is set when a character is transferred into
UxRXBUF before the previous character was read.
0
1
BRK Bit 4 Break detect flag
0
1
URXEIE Bit 3 Receive erroneous-character interrupt-enable
0
1
URXWIE Bit 2 Receive wake-up interrupt-enable. This bit enables URXIFGx to be set
when an address character is received. When URXEIE = 0, an address
character will not set URXIFGx if it is received with errors.
0
1
RXWAKE Bit 1 Receive wake-up flag
0
1
RXERR Bit 0 Receive error flag. This bit indicates a character was received with error(s).
When RXERR = 1, on or more error flags (FE,PE,OE, BRK) is also set.
RXERR is cleared when UxRXBUF is read.
0
1
13-24
USART Peripheral Interface, UART Mode
5 4 3
OE BRK URXEIE
rw−0 rw−0 rw−0
No error
Character received with low stop bit
No error
Character received with parity error
No error
Overrun error occurred
No break condition
Break condition occurred
Erroneous characters rejected and URXIFGx is not set
Erroneous characters received will set URXIFGx
All received characters set URXIFGx
Only received address characters set URXIFGx
Received character is data
Received character is an address
No receive errors detected
Receive error detected
2 1
URXWIE RXWAKE RXERR
rw−0 rw−0 rw−0
0