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* DINT
Disable (general) interrupts
Syntax
DINT
0 → GIE
Operation
or
(0FFF7h .AND. SR → SR
Emulation
BIC
Description
All interrupts are disabled.
The constant 08h is inverted and logically ANDed with the status register (SR).
The result is placed into the SR.
Status Bits
Status bits are not affected.
Mode Bits
GIE is reset. OSCOFF and CPUOFF are not affected.
Example
The general interrupt enable (GIE) bit in the status register is cleared to allow
a nondisrupted move of a 32-bit counter. This ensures that the counter is not
modified during the move by any interrupt.
DINT
NOP
MOV
MOV
EINT
Note: Disable Interrupt
If any code sequence needs to be protected from interruption, the DINT
should be executed at least one instruction before the beginning of the
uninterruptible sequence, or should be followed by a NOP instruction.
/
.NOT.src .AND. dst −> dst)
#8,SR
; All interrupt events using the GIE bit are disabled
COUNTHI,R5
; Copy counter
COUNTLO,R6
; All interrupt events using the GIE bit are enabled
Instruction Set
RISC 16−Bit CPU
3-39
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