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Figure 18−12. State Diagram for Data Transfer Control in Two-Block Transfer Mode
n = 0
Write to ADC10SA
or
n = 0
Write to ADC10SA
Write to ADC10SA
n=0 (ADC10DTC1)
DTC reset
ADC10B1 = 0
ADC10TB = 1
n ≠ 0
Wait for write to
ADC10SA
Initialize
Start Address in ADC10SA
DTC init
Write to
ADC10SA
x = n
If ADC10B1 = 0
n is latched
then AD = SA
in counter 'x'
Wait until ADC10MEM
is written
DTC idle
Write to ADC10MEM
completed
Wait
Synchronize
for
with MCLK
CPU ready
1 x MCLK cycle
Transfer data to
Address AD
AD = AD + 2
x = x − 1
ADC10B1 = 1
x = 0
ADC10CT=1
ADC10IFG=1
Toggle
ADC10B1
ADC10 Operation
Prepare
DTC
x > 0
DTC
operation
or
ADC10CT = 0
and
ADC10B1 = 0
ADC10
18-19
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