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Figure 10−1. Watchdog Timer Block Diagram
WDTQn
Int.
Flag
Pulse
Generator
PUC
SMCLK
ACLK
Q6
4
Q9
3
Y
Q13
2
Q15
1
16−bit
Counter
A
B
Clear
CLK
(Asyn)
1
1
A
EN
Watchdog Timer Introduction
WDTCTL
MSB
0
1
0
1
Password
Compare
1
0
1
0
EQU
Write Enable
Low Byte
EQU
WDTHOLD
WDTNMIES
WDTNMI
WDTTMSEL
WDTCNTCL
WDTSSEL
WDTIS1
WDTIS0
LSB
Watchdog Timer
MDB
16−bit
R / W
10-3
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