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DCOCTL, DCO Control Register
7
6
DCOx
rw−0
rw−1
DCOx
Bits
DCO frequency select. These bits select which of the eight discrete DCO
7-5
frequencies of the RSELx setting is selected.
MODx
Bits
Modulator selection. These bits define how often the f
4-0
used within a period of 32 DCOCLK cycles. During the remaining clock
cycles (32−MOD) the f
BCSCTL1, Basic Clock System Control Register 1
7
6
XT2OFF
XTS
rw−(1)
rw−(0)
XT2OFF
Bit 7
XT2 off. This bit turns off the XT2 oscillator
0
1
XTS
Bit 6
LFXT1 mode select.
0
1
DIVAx
Bits
Divider for ACLK
5-4
00
01
10
11
XT5V
Bit 3
Unused. XT5V should always be reset.
RSELx
Bits
Resistor Select. The internal resistor is selected in eight different steps.
2-0
The value of the resistor defines the nominal frequency. The lowest
nominal frequency is selected by setting RSELx=0.
5
4
rw−1
rw−0
rw−0
frequency is used. Not useable when DCOx=7.
DCO
5
4
DIVAx
XT5V
rw−(0)
rw−(0)
rw−0
XT2 is on
XT2 is off if it is not used for MCLK or SMCLK.
Low frequency mode
High frequency mode
/1
/2
/4
/8
Basic Clock Module Registers
3
2
1
MODx
rw−0
rw−0
DCO+1
3
2
1
RSELx
rw−1
rw−0
Basic Clock Module
0
rw−0
frequency is
0
rw−0
4-15
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