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U0CTL, USART0 Control Register-I
7
6
RXDMAEN
TXDMAEN
rw−0
rw−0
RXDMAEN
Bit 7
Receive DMA enable. This bit enables the DMA controller to be used to
transfer data from the I
RXDMAEN = 1, RXRDYIE is ignored.
0
1
TXDMAEN
Bit 6
Transmit DMA enable. This bit enables the DMA controller to be used to
provide data to the I
TXRDYIE, is ignored.
0
1
2
I2C
Bit 5
I
C mode enable. This bit select I
0
1
XA
Bit 4
Extended Addressing
0
1
LISTEN
Bit 3
Listen. This bit selects loopback mode. LISTEN is only valid when MST = 1
and I2CTRX = 1 (master transmitter).
0
1
SYNC
Bit 2
Synchronous mode enable
0
1
MST
Bit 1
Master. This bit selects master or slave mode. The MST bit is automatically
cleared when arbitration is lost or a STOP condition is generated.
0
1
2
I2CEN
Bit 0
I
C enable. The bit enables or disables the I
for this bit is set, and SWRST function for UART or SPI. When the I2C and
SYNC bits are first set after a PUC, this bit becomes I2CEN function and is
automatically cleared.
0
1
2
C Mode
5
4
3
I2C
XA
LISTEN
rw−0
rw−0
rw−0
2
C module after the I
Disabled
Enabled
2
C module for transmission. When TXDMAEN = 1,
Disabled
Enabled
SPI mode
2
I
C mode
7-bit addressing
10-bit addressing
Normal mode
SDA is internally fed back to the receiver (loopback).
UART mode
2
SPI or I
C mode
Slave mode
Master mode
2
I
C operation is disabled
2
I
C operation is enabled
USART Peripheral Interface, I
2
I
C Module Registers
2
1
SYNC
MST
rw−0
rw−0
2
C modules receives data. When
2
C or SPI operation when SYNC = 1.
2
C module. The initial condition
2
C Mode
0
I2CEN
rw−1
15-21
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