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Timer_B Control Register TBCTL
15
14
Unused
TBCLGRPx
rw−(0)
rw−(0)
7
6
IDx
rw−(0)
rw−(0)
Unused
Bit 15
Unused
TBCLGRP
Bit
TBCLx group
14-13
00
01
10
11
CNTLx
Bits
Counter Length
12-11
00
01
10
11
Unused
Bit 10
Unused
TBSSELx
Bits
Timer_B clock source select.
9-8
00
01
10
11
IDx
Bits
Input divider. These bits select the divider for the input clock.
7-6
00
01
10
11
MCx
Bits
Mode control. Setting MCx = 00h when Timer_B is not in use conserves
5-4
power.
00
01
10
11
13
12
11
CNTLx
rw−(0)
rw−(0)
rw−(0)
5
4
MCx
Unused
rw−(0)
rw−(0)
rw−(0)
Each TBCLx latch loads independently
TBCL1+TBCL2 (TBCCR1 CLLDx bits control the update)
TBCL3+TBCL4 (TBCCR3 CLLDx bits control the update)
TBCL5+TBCL6 (TBCCR5 CLLDx bits control the update)
TBCL0 independent
TBCL1+TBCL2+TBCL3 (TBCCR1 CLLDx bits control the update)
TBCL4+TBCL5+TBCL6 (TBCCR4 CLLDx bits control the update)
TBCL0 independent
TBCL0+TBCL1+TBCL2+TBCL3+TBCL4+TBCL5+TBCL6
(TBCCR1 CLLDx bits control the update)
16-bit, TBR
= 0FFFFh
(max)
12-bit, TBR
= 0FFFh
(max)
10-bit, TBR
= 03FFh
(max)
8-bit, TBR
= 0FFh
(max)
TBCLK
ACLK
SMCLK
Inverted TBCLK
/1
/2
/4
/8
Stop mode: the timer is halted
Up mode: the timer counts up to TBCL0
Continuous mode: the timer counts up to the value set by TBCNTLx
Up/down mode: the timer counts up to TBCL0 and down to 0000h
10
9
Unused
rw−(0)
rw−(0)
3
2
1
TBCLR
TBIE
w−(0)
rw−(0)
Timer_B
Timer_B Registers
8
TBSSELx
rw−(0)
0
TBIFG
rw−(0)
12-21
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