Texas Instruments MSP430x1xx User Manual page 187

DMACTL0, DMA Control Register 0
15 14
Reserved
rw−(0) rw−(0)
7 6
DMA1TSELx
rw−(0) rw−(0)
Reserved Bits Reserved
15−12
DMA2 Bits DMA trigger select. These bits select the DMA transfer trigger.
TSELx
11−8 0000 DMAREQ bit (software trigger)
0001 TACCR2 CCIFG bit
0010 TBCCR2 CCIFG bit
0011 URXIFG0 (UART/SPI mode), USART0 data received (I
0100 UTXIFG0 (UART/SPI mode), USART0 transmit ready (I
0101 DAC12_0CTL DAC12IFG bit
0110 ADC12 ADC12IFGx bit
0111 TACCR0 CCIFG bit
1000 TBCCR0 CCIFG bit
1001 URXIFG1 bit
1010 UTXIFG1 bit
1011 Multiplier ready
1100 No action
1101 No action
1110 DMA0IFG bit triggers DMA channel 1
1111 External trigger DMAE0
DMA1 Bits Same as DMA2TSELx
TSELx
7−4
DMA0 Bits Same as DMA2TSELx
TSELx
3–0
13 12 11
rw−(0) rw−(0) rw−(0)
5 4
rw−(0) rw−(0) rw−(0)
DMA1IFG bit triggers DMA channel 2
DMA2IFG bit triggers DMA channel 0
10 9
DMA2TSELx
rw−(0) rw−(0)
3 2 1
DMA0TSELx
rw−(0) rw−(0)
8
rw−(0)
0
rw−(0)
2
C mode)
2
C mode)
8-19