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FCTL2, Flash Memory Control Register
15
14
7
6
FSSELx
rw−0
rw−1
FWKEYx
Bits
FCTLx password. Always read as 096h. Must be written as 0A5h or a PUC
15-8
will be generated.
FSSELx
Bits
Flash controller clock source select
7−6
00
01
10
11
FNx
Bits
Flash controller clock divider. These six bits select the divider for the flash
5-0
controller clock. The divisor value is FNx + 1. For example, when FNx=00h,
the divisor is 1. When FNx=03Fh the divisor is 64.
13
12
11
FWKEYx, Read as 096h
Must be written as 0A5h
5
4
3
rw-0
rw-0
rw-0
ACLK
MCLK
SMCLK
SMCLK
Flash Memory Registers
10
9
2
1
FNx
rw−0
rw-1
Flash Memory Controller
8
0
rw−0
5-19
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