Texas Instruments MSP430x1xx User Manual page 306

UxTCTL, USART Transmit Control Register
7 6
CKPH CKPL
rw−0 rw−0
CKPH
Bit 7 Clock phase select. Controls the phase of UCLK.
0
1
CKPL Bit 6 Clock polarity select
0
1
SSELx Bits Source select. These bits select the BRCLK source clock.
5-4 00
01
10
11
Unused Bit 3 Unused
Unused Bit 2 Unused
STC Bit 1 Slave transmit control.
0
1
TXEPT Bit 0 Transmitter empty flag. The TXEPT flag is not used in slave mode.
0
1
5 4 3
SSELx Unused
rw−0 rw−0 rw−0
Normal UCLK clocking scheme
UCLK is delayed by one half cycle
The inactive level is low; data is output with the rising edge of UCLK;
input data is latched with the falling edge of UCLK.
The inactive level is high; data is output with the falling edge of
UCLK; input data is latched with the rising edge of UCLK.
External UCLK (valid for slave mode only)
ACLK (valid for master mode only)
SMCLK (valid for master mode only)
SMCLK (valid for master mode only)
4-pin SPI mode: STE enabled.
3-pin SPI mode: STE disabled.
Transmission active and/or data waiting in UxTXBUF
UxTXBUF and TX shift register are empty
USART Peripheral Interface, SPI Mode
USART Registers: SPI Mode
2 1
Unused STC TXEPT
rw−0 rw−0 rw−1
0
14-15