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Transmit Bit Timing
The timing for each character is the sum of the individual bit timings. By
modulating each bit, the cumulative bit error is reduced. The individual bit error
can be calculated by:
With:
For example, the transmit errors for the following conditions are calculated:
Start bit Error [%] + baud rate
Data bit D0 Error [%] + baud rate
Data bit D1 Error [%] + baud rate
Data bit D2 Error [%] + baud rate
Data bit D3 Error [%] + baud rate
Data bit D4 Error [%] + baud rate
Data bit D5 Error [%] + baud rate
Data bit D6 Error [%] + baud rate
Data bit D7 Error [%] + baud rate
Parity bit Error [%] + baud rate
Stop bit 1 Error [%] + baud rate
The results show the maximum per-bit error to be 5.08% of a BITCLK period.
Error [%] + baud rate
BRCLK
baud rate: Desired baud rate
BRCLK:
Input frequency − UCLKI, ACLK, or SMCLK
j:
Bit position - 0 for the start bit, 1 for data bit D0, and so on
UxBR:
Division factor in registers UxBR1 and UxBR0
Baud rate =
2400
BRCLK =
32,768 Hz (ACLK)
UxBR =
13, since the ideal division factor is 13.65
UxMCTL =
6Bh: m7 = 0, m6 = 1, m5 = 1, m4 = 0, m3 = 1, m2 = 0,
m1 = 1, and m0= 1. The LSB of UxMCTL is used first.
(( 0 ) 1 )
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
BRCLK
USART Peripheral Interface, UART Mode
USART Operation: UART Mode
j
( j ) 1 )
UxBR ) S
m
i
i+0
UxBR ) 1 ) –1
100% + 2.54%
(( 1 ) 1 )
UxBR ) 2 ) –2
(( 2 ) 1 )
UxBR ) 2 ) –3
(( 3 ) 1 )
UxBR ) 3 ) –4
(( 4 ) 1 )
UxBR ) 3 ) –5
(( 5 ) 1 )
UxBR ) 4 ) –6
(( 6 ) 1 )
UxBR ) 5 ) –7
(( 7 ) 1 )
UxBR ) 5 ) –8
(( 8 ) 1 )
UxBR ) 6 ) –9
(( 9 ) 1 )
UxBR ) 7 ) –10
(( 10 ) 1 )
UxBR ) 7 ) –11
* ( j ) 1 )
100%
100% + 5.08%
100% + 0.29%
100% + 2.83%
100% +*1.95%
100% + 0.59%
100% + 3.13%
100% + *1.66%
100% + 0.88%
100% + 3.42%
100% + *1.37%
13-13
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