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TBCCTLx, Capture/Compare Control Register
15
14
CMx
rw−(0)
rw−(0)
7
6
OUTMODx
rw−(0)
rw−(0)
CMx
Bit
Capture mode
15-14
00
01
10
11
CCISx
Bit
Capture/compare input select. These bits select the TBCCRx input signal.
13-12
See the device-specific datasheet for specific signal connections.
00
01
10
11
SCS
Bit 11
Synchronize capture source. This bit is used to synchronize the capture input
signal with the timer clock.
0
1
CLLDx
Bit
Compare latch load. These bits select the compare latch load event.
10-9
00
01
10
11
CAP
Bit 8
Capture mode
0
1
OUTMODx
Bits
Output mode. Modes 2, 3, 6, and 7 are not useful for TBCL0 because EQUx
7-5
= EQU0.
000 OUT bit value
001 Set
010 Toggle/reset
011 Set/reset
100 Toggle
101 Reset
110 Toggle/set
111 Reset/set
13
12
11
CCISx
SCS
rw−(0)
rw−(0)
rw−(0)
5
4
CCIE
CCI
rw−(0)
rw−(0)
No capture
Capture on rising edge
Capture on falling edge
Capture on both rising and falling edges
CCIxA
CCIxB
GND
V
CC
Asynchronous capture
Synchronous capture
TBCLx loads on write to TBCCRx
TBCLx loads when TBR counts to 0
TBCLx loads when TBR counts to 0 (up or continuous mode)
TBCLx loads when TBR counts to TBCL0 or to 0 (up/down mode)
TBCLx loads when TBR counts to TBCLx
Compare mode
Capture mode
10
9
CLLDx
rw−(0)
r−(0)
3
2
1
OUT
COV
r
rw−(0)
rw−(0)
Timer_B
Timer_B Registers
8
CAP
rw−(0)
0
CCIFG
rw−(0)
12-23
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