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Timer_A Registers
TACTL, Timer_A Control Register
15
14
rw−(0)
rw−(0)
7
6
IDx
rw−(0)
rw−(0)
Unused
Bits
Unused
15-10
TASSELx
Bits
Timer_A clock source select
9-8
00
01
10
11
IDx
Bits
Input divider. These bits select the divider for the input clock.
7-6
00
01
10
11
MCx
Bits
Mode control. Setting MCx = 00h when Timer_A is not in use conserves
5-4
power.
00
01
10
11
Unused
Bit 3
Unused
TACLR
Bit 2
Timer_A clear. Setting this bit resets TAR, the TACLK divider, and the count
direction. The TACLR bit is automatically reset and is always read as zero.
TAIE
Bit 1
Timer_A interrupt enable. This bit enables the TAIFG interrupt request.
0
1
TAIFG
Bit 0
Timer_A interrupt flag
0
1
11-20
Timer_A
13
12
11
Unused
rw−(0)
rw−(0)
rw−(0)
5
4
MCx
Unused
rw−(0)
rw−(0)
rw−(0)
TACLK
ACLK
SMCLK
INCLK
/1
/2
/4
/8
Stop mode: the timer is halted
Up mode: the timer counts up to TACCR0
Continuous mode: the timer counts up to 0FFFFh
Up/down mode: the timer counts up to TACCR0 then down to 0000h
Interrupt disabled
Interrupt enabled
No interrupt pending
Interrupt pending
10
9
rw−(0)
rw−(0)
3
2
1
TACLR
TAIE
w−(0)
rw−(0)
8
TASSELx
rw−(0)
0
TAIFG
rw−(0)
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