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USART Operation: SPI Mode
Serial Clock Polarity and Phase
The polarity and phase of UCLK are independently configured via the CKPL
and CKPH control bits of the USART. Timing for each case is shown in
Figure 14−9.
Figure 14−9. USART SPI Timing
Cycle#
CKPH CKPL
0
0
UCLK
0
1
UCLK
1
0
UCLK
1
1
UCLK
STE
SIMO/
0
X
SOMI
SIMO/
1
X
SOMI
Move to UxTXBUF
TX Data Shifted Out
RX Sample Points
14-10
USART Peripheral Interface, SPI Mode
1
2
3
MSB
MSB
4
5
6
7
8
LSB
LSB
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