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2
I2CDCTL, I
C Data Control Register
7
6
Unused
Unused
r0
r0
Unused
Bits
Unused. Always read as 0.
7−6
2
I2CBUSY
Bit 5
I
C busy
0
1
2
I2C
Bit 4
I
C SCL low. This bit indicates if a slave is holding the SCL line low while the
SCLLOW
MSP430 is the master and is unused in slave mode.
0
1
2
I2CSBD
Bit 3
I
C single byte data. This bit indicates if the receive register I2CDRW holds
a word or a byte. I2CSBD is valid only when I2CWORD = 1.
0
1
2
I2CTXUDF
Bit 2
I
C transmit underflow
0
1
2
I2CRXOVR
Bit 1
I
C receive overrun
0
1
2
I2CBB
Bit 0
I
C bus busy bit. A START condition sets I2CBB to 1. I2CBB is reset by a
STOP condition or when I2CEN=0.
0
1
5
4
I2C
I2CBUSY
I2CSBD
SCLLOW
r−0
r−0
2
I
C module is idle
2
I
C module is not idle
SCL is not being held low
SCL is being held low
A complete word was received
Only the lower byte in I2CDR is valid
No underflow occurred
Transmit underflow occurred
No receive overrun occurred
Receiver overrun occurred
2
I
C bus not busy
2
I
C bus busy
USART Peripheral Interface, I
I
3
2
1
I2CTXUDF
I2CRXOVR
r−0
r−0
r−0
2
2
C Module Registers
0
I2CBB
r−0
C Mode
15-23
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