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Initiating an Erase from RAM
Any erase cycle may be initiated from RAM. In this case, the CPU is not held
and can continue to execute code from RAM. The BUSY bit must be polled to
determine the end of the erase cycle before the CPU can access any flash
address again. If a flash access occurs while BUSY=1, it is an access violation,
ACCVIFG will be set, and the erase results will be unpredictable.
The flow to initiate an erase from flash from RAM is shown in Figure 5−6.
Figure 5−6. Erase Cycle from Within RAM
; Segment Erase from RAM. 514 kHz < SMCLK < 952 kHz
; Assumes ACCVIE = NMIIE = OFIE = 0.
L1 BIT
L2 BIT
Disable all interrupts and watchdog
yes
BUSY = 1
Setup flash controller and
erase mode
Dummy write
yes
BUSY = 1
Set LOCK = 1, re-enable
interrupts and watchdog
MOV
#WDTPW+WDTHOLD,&WDTCTL
DINT
#BUSY,&FCTL3
JNZ
L1
MOV
#FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2
MOV
#FWKEY,&FCTL3
MOV
#FWKEY+ERASE,&FCTL1
CLR
&0FC10h
#BUSY,&FCTL3
JNZ
L2
MOV
#FWKEY+LOCK,&FCTL3
...
EINT
Flash Memory Operation
; Disable WDT
; Disable interrupts
; Test BUSY
; Loop while busy
; Clear LOCK
; Enable erase
; Dummy write, erase S1
; Test BUSY
; Loop while busy
; Done, set LOCK
; Re-enable WDT?
; Enable interrupts
Flash Memory Controller
5-7
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