Texas Instruments MSP430x1xx User Manual page 297

USART Operation: SPI Mode
14.2.3 Slave Mode
Figure 14−3. USART Slave and External Master
MASTER
SPI Receive Buffer
Data Shift Register DSR
MSB
LSB
SCLK
COMMON SPI
Figure 14−3 shows the USART as a slave in both 3-pin and 4-pin
configurations. UCLK is used as the input for the SPI clock and must be
supplied by the external master. The data-transfer rate is determined by this
clock and not by the internal baud rate generator. Data written to UxTXBUF
and moved to the TX shift register before the start of UCLK is transmitted on
SOMI. Data on SIMO is shifted into the receive shift register on the opposite
edge of UCLK and moved to UxRXBUF when the set number of bits are
received. When data is moved from the RX shift register to UxRXBUF, the
URXIFGx interrupt flag is set, indicating that data has been received. The
overrun error bit, OE, is set when the previously received data is not read from
UxRXBUF before new data is moved to UxRXBUF.
Four-Pin SPI Slave Mode
In 4-pin slave mode, STE is used by the slave to enable the transmit and
receive operations and is provided by the SPI master. When STE is low, the
slave operates normally. When STE is high:
-
-
A high STE signal does not reset the USART module. The STE input signal
is not used in 3-pin slave mode.
14-6
USART Peripheral Interface, SPI Mode
SIMO SIMO
Transmit Buffer UxTXBUF
Px.x STE
SS
STE
Port.x
SOMI SOMI
Transmit Shift Register
MSB
UCLK
Any receive operation in progress on SIMO is halted
SOMI is set to the input direction
SLAVE
Receive Buffer UxRXBUF
Receive Shift Register
MSB
LSB
MSP430 USART
LSB