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Timer_B Operation
Figure 12−11.Capture Cycle
Clear Bit COV
in Register TBCCTLx
Capture Initiated by Software
Captures can be initiated by software. The CMx bits can be set for capture on
both edges. Software then sets bit CCIS1=1 and toggles bit CCIS0 to switch
the capture signal between V
CCIS0 changes state:
Compare Mode
The compare mode is selected when CAP = 0. Compare mode is used to
generate PWM output signals or interrupts at specific time intervals. When
TBR counts to the value in a TBCLx:
-
-
-
12-12
Timer_B
Capture
No
Capture
Taken
MOV
#CAP+SCS+CCIS1+CM_3,&TBCCTLx ; Setup TBCCTLx
XOR
#CCIS0,&TBCCTLx
Interrupt flag CCIFG is set
Internal signal EQUx = 1
EQUx affects the output according to the output mode
Idle
Capture Read
Capture
Taken
Capture
Capture Read and No Capture
Capture
Second
Capture
Idle
Taken
COV = 1
and GND, initiating a capture each time
CC
; TBCCTLx = TBR
Read
Taken
Capture
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