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2
I2CPSC, I
C Clock Prescaler Register
7
6
rw−0
rw−0
Modifiable only when I2CEN = 0
2
I2CPSCx
Bits
I
C clock prescaler. The I
7−0
to produce the internal I
I2CPSCx values > 4 are not recommended. The I2CSCLL and I2CSCLH
registers should be used to set the SCL frequency.
000h Divide by 1
001h Divide by 2
:
0FFh Divide by 256
5
4
3
I2CPSCx
rw−0
rw−0
rw−0
2
C clock input I2CIN is divided by the I2CPSCx value
2
C clock frequency. The division rate is I2CPSCx+1.
USART Peripheral Interface, I
2
I
C Module Registers
2
1
0
rw−0
rw−0
rw−0
2
C Mode
15-25
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