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USART Operation: UART Mode
Receive Bit Timing
Receive timing consists of two error sources. The first is the bit-to-bit timing
error. The second is the error between a start edge occurring and the start
edge being accepted by the USART. Figure 13−9 shows the asynchronous
timing errors between data on the URXDx pin and the internal baud-rate clock.
Figure 13−9. Receive Error
i
t
ideal
1 2 3 4 5 6
BRCLK
URXDx
URXDS
t
actual
Synchronization Error ± 0.5x BRCLK
Sample
URXDS
Int(UxBR/2)+m0 =
Int (13/2)+1 = 6+1 = 7
The ideal start bit timing t
the bit is tested in the middle of its period. The ideal baud rate timing t
the remaining character bits is the baud rate timing t
errors can be calculated by:
Error [%] + baud rate
BRCLK
Where:
baud rate is the required baud rate
BRCLK is the input frequency—selected for UCLK, ACLK, or SMCLK
j = 0 for the start bit, 1 for data bit D0, and so on
UxBR is the division factor in registers UxBR1 and UxBR0
13-14
USART Peripheral Interface, UART Mode
0
t 0
7 8
9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7
ST
ST
t 0
UxBR +m1 = 13+1 = 14
Majority Vote Taken
ideal(0)
m0 ) int UxBR
2
2
1
t 1
D0
D0
t 1
UxBR +m2 = 13+0 = 13
Majority Vote Taken
is half the baud-rate timing t
baud rate
j
) i
UxBR ) S
m
i
i+1
2
D1
D1
t 2
Majority Vote Taken
because
baud rate
for
ideal(i)
. The individual bit
* 1 * j
100%
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