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ADC10CTL0, ADC10 Control Register 0
15
14
SREFx
rw−(0)
rw−(0)
7
6
MSC
REF2_5V
rw−(0)
rw−(0)
Modifiable only when ENC = 0
SREFx
Bits
Select reference
15-13
000 V
001 V
010 V
011 V
100 V
101 V
110 V
111 V
ADC10
Bits
ADC10 sample-and-hold time
SHTx
12-11
00
01
10
11
ADC10SR
Bit 10
ADC10 sampling rate. This bit selects the reference buffer drive capability for
the maximum sampling rate. Setting ADC10SR reduces the current
consumption of the reference buffer.
0
1
REFOUT
Bit 9
Reference output
0
1
REFBURST
Bit 8
Reference burst. REFOUT must also be set.
0
1
13
12
ADC10SHTx
rw−(0)
rw−(0)
rw−(0)
5
4
REFON
ADC10ON
ADC10IE
rw−(0)
rw−(0)
rw−(0)
= V
and V
= V
R+
CC
R−
SS
= V
and V
= V
R+
REF+
R−
= Ve
and V
= V
R+
REF+
R−
= Ve
and V
= V
R+
REF+
R−
= V
and V
= V
R+
CC
R−
REF−
= V
and V
= V
R+
REF+
R−
= Ve
and V
= V
R+
REF+
R−
= Ve
and V
= V
R+
REF+
R−
4 x ADC10CLKs
8 x ADC10CLKs
16 x ADC10CLKs
64 x ADC10CLKs
Reference buffer supports up to ~200 ksps
Reference buffer supports up to ~50 ksps
Reference output off
Reference output on
Reference buffer on continuously
Reference buffer on only during sample-and-conversion
11
10
9
ADC10SR
REFOUT
rw−(0)
rw−(0)
3
2
1
ADC10IFG
ENC
rw−(0)
rw−(0)
SS
SS
SS
/ Ve
REF−
/ Ve
REF−
REF−
/ Ve
REF−
REF−
/ Ve
REF−
REF−
ADC10 Registers
8
REFBURST
rw−(0)
0
ADC10SC
rw−(0)
ADC10
18-25
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