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Flash Memory Operation
Initiating an Erase from Within Flash Memory
Any erase cycle can be initiated from within flash memory or from RAM. When
a flash segment erase operation is initiated from within flash memory, all timing
is controlled by the flash controller, and the CPU is held while the erase cycle
completes. After the erase cycle completes, the CPU resumes code execution
with the instruction following the dummy write.
When initiating an erase cycle from within flash memory, it is possible to erase
the code needed for execution after the erase. If this occurs, CPU execution
will be unpredictable after the erase cycle.
The flow to initiate an erase from flash is shown in Figure 5−5.
Figure 5−5. Erase Cycle from Within Flash Memory
; Segment Erase from flash. 514 kHz < SMCLK < 952 kHz
; Assumes ACCVIE = NMIIE = OFIE = 0.
5-6
Flash Memory Controller
Disable all interrupts and watchdog
Setup flash controller and erase
mode
Dummy write
Set LOCK=1, re-enable Interrupts
and watchdog
MOV
#WDTPW+WDTHOLD,&WDTCTL
DINT
MOV
#FWKEY+FSSEL1+FN0,&FCTL2 ; SMCLK/2
MOV
#FWKEY,&FCTL3
MOV
#FWKEY+ERASE,&FCTL1
CLR
&0FC10h
MOV
#FWKEY+LOCK,&FCTL3
...
EINT
; Disable WDT
; Disable interrupts
; Clear LOCK
; Enable segment erase
; Dummy write, erase S1
; Done, set LOCK
; Re-enable WDT?
; Enable interrupts
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