Table of Contents
Advertisement
USART Registers: SPI Mode
UxRXBUF, USART Receive Buffer Register
7
6
2 7
2 6
r
r
UxRXBUFx
Bits
The receive-data buffer is user accessible and contains the last received
7−0
character from the receive shift register. Reading UxRXBUF resets the OE
bit and URXIFGx flag. In 7-bit data mode, UxRXBUF is LSB justified and
the MSB is always reset.
UxTXBUF, USART Transmit Buffer Register
7
6
2 7
2 6
rw
rw
UxTXBUFx
Bits
The transmit data buffer is user accessible and contains current data to be
7−0
transmitted. When seven-bit character-length is used, the data should be
MSB justified before being moved into UxTXBUF. Data is transmitted MSB
first. Writing to UxTXBUF clears UTXIFGx.
14-18
USART Peripheral Interface, SPI Mode
5
4
3
2 5
2 4
2 3
r
r
r
5
4
3
2 5
2 4
2 3
rw
rw
rw
2
1
0
2 2
2 1
2 0
r
r
r
2
1
0
2 2
2 1
2 0
rw
rw
rw
Advertisement
Table of Contents
