Table of Contents
Advertisement
USART Operation: SPI Mode
Receive Enable
The SPI receive enable state diagrams are shown in Figure 14−6 and
Figure 14−7. When USPIEx = 0, UCLK is disabled from shifting data into the
RX shift register.
Figure 14−6. SPI Master Receive-Enable State Diagram
USPIEx = 0
Receive
Disable
SWRST
PUC
Figure 14−7. SPI Slave Receive-Enable State Diagram
USPIEx = 0
Receive
Disable
SWRST
PUC
14-8
USART Peripheral Interface, SPI Mode
No Data Written
to UxTXBUF
USPIEx = 1
Idle State
(Receiver
Enabled)
Data Written
USPIEx = 0
to UxTXBUF
USPIEx = 0
No Clock at UCLK
USPIEx = 1
Idle State
(Receive
External Clock
Enabled)
USPIEx = 0
Present
USPIEx = 0
Not Completed
Receiver
USPIEx = 1
Collects
Character
USPIEx = 1
Not Completed
Receiver
USPIEx = 1
Collects
Character
USPIEx = 1
Handle Interrupt
Conditions
Character
Received
Handle Interrupt
Conditions
Character
Received
Advertisement
Table of Contents
