Multiple Cpu High-Speed Transmission Dedicated Instruction - Mitsubishi MELSEC Q Series Programming Manual

2.8
Multiple CPU high-speed transmission dedicated
instruction
2.8.1
Instructions for Multiple CPU high-speed transmission
dedicated
Category
D.DDWR
Writing Devices
to Another CPU
DP.DDWR
D.DDRD
Reading Devices
from Another
CPU
DP.DDRD
Table 2.40 Multiple CPU high-speed transmission dedicated instruction
Symbol
D.DDWR S1 S2 D1 D2
n
DP.DDWR n S1 S2 D1 D2
D.DDRD S1 S2 D1 D2
n
DP.DDRD n S1 S2 D1 D2
Processing Details
In multiple CPU system, data stored in a
S2
device specified by host CPU ( ) or later is
stored by the number of write points specified
D2
by ( +1) into a device specified by another
CPU (n) ( ) or later
D1
In multiple CPU system, data stored in a
device specified by another CPU (n) (
lrater is stored by the number of read points
S1
specified by ( +1) into a device specified by
S2
host CPU ( ) or late
Execution
Condition
10 -
10 -
10 -
) or
D1
10 -
1
2
4
4
2
6
10-13
7
8
10-17
2-61