Association Instructions - Mitsubishi MELSEC Q Series Programming Manual

*2: The number of steps may vary depending on the device and type of CPU module being used.
The number of steps may vary depending on the device being used.
2.3.2

Association instructions

Category
ANB
ORB
MPS
MPS
MRD
MRD
MPP MPP
Connec-
INV
tion
MEP
MEF
EGP
EGF
*1: The number of steps may vary depending on the device and type of CPU module being used.
Internal device, file register (R0 to R32767)
Direct access input (DX)
Devices other than above
Internal device, file register (R0 to R32767)
Serial number access format file register (ZR), Extended data register (D),
Extended link register (W), Multiple CPU shared device (U3En\G10000)
Direct access input (DX)
Devices other than above
Table 2.4 Association Instructions
Symbol
• AND between logical blocks
ANB (Series connection between logical blocks)
• OR between logical blocks
(Series connection between logical blocks)
ORB
• Memory storage of operation results
• Read of operation results stored with MPS
instruction
• Read and reset of operation results stored with
MPS instruction
• Inversion of operation result
• Conversion of operation result to leading edge
pulse
• Conversion of operation result to trailing edge
pulse
• Conversion of operation result to leading edge
Vn
pulse
(Stored at Vn)
• Conversion of operation result to trailing edge
Vn
pulse
(Stored at Vn)
Component
High Performance model QCPU
Process CPU
Redundant CPU
Universal model QCPU
LCPU
Basic model QCPU
Device
Device
Processing Details
Number of Basic Steps
Number of Steps
1
1
3
Number of Steps
Number of Basic Steps
Number of Basic Steps +1
Number of Basic Steps +1
Number of Basic Steps +2
Execution
Condition
1 - 5-10
1 - 5-12
1 - 5-15
1 - 5-17
1
- 5-18
*1
1
2
2-7
2
3
4
4
6
7
8