Mitsubishi MELSEC Q Series Programming Manual page 53

Category
BXCH
Block data
exchange
BXCHP
Exchange
SWAP
of upper
and lower
SWAPP
bytes
*1: The number of steps may vary depending on the device and type of CPU module being used.
Component
QCPU
LCPU
*2: The number of steps may vary depending on the device and type of CPU module being used.
Component
High Performance model QCPU
Process CPU
Redundant CPU
Basic model QCPU
Universal model QCPU
LCPU
Table 2.13 Data Transfer Instructions (Continued)
Symbol
BXCH S D n
BXCHP S D n
SWAP D
SWAPP D
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
designation is K4, and which use no indexing.
• Constant: No limitations
Devices other than above
Note 1) The number of steps may increase due to the conditions described in Section 3.8.
• Word device: Internal device (except for file register ZR)
• Bit device:
• Constant:
Devices other than above
• Word device: Int
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing.
• Constant: No limitations
(The number of steps is 3 when the above device + constant are used.)
Devices other than above
All devices that can be used
Note 1) The number of steps may increase due to the conditions described in Section 3.8.
Processing Details
(S) (D)
n
b15 to b8 b7 to b0
(S)
8 bits 8 bits
b15 to b8 b7 to b0
(D) 8 bits 8 bits
Device
Device
Devices whose device Nos. are multiples of 16, whose
digit designation is K8, and which use no
No limitations
ernal device (except for file register ZR)
Execution
Condition
4 - 6-129
3 - 6-131
Number of
Steps
2
Note 1)
3
Number of
Steps
3
.
indexing
Note 1)
3
2
Note 1)
3
Note 1)
2
2-25
2
3
4
4
6
7
8