Mitsubishi MELSEC Q Series Programming Manual page 965

Error
Error Contents and Cause
Code
[PARAMETER ERROR]
The parameter-set number of CPU modules differs
from the actual number in a multiple CPU system.
■Collateral information
• Common information: File name/Drive name
3010
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
Multiple CPU setting or control CPU setting differs
from that of the reference CPU settings in a
multiple CPU system.
■Collateral information
3012
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
Multiple CPU auto refresh setting is any of the
followings in a multiple CPU system.
• When a bit device is specified as a refresh
device, a number other than a multiple of 16 is
specified for the refresh-starting device.
• The device specified is other than the one that
may be specified.
• The number of send points is an odd number.
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
In a multiple CPU system, the multiple CPU auto
refresh setting is any of the following.
• The total number of transmission points is
greater than the maximum number of refresh
points.
■Collateral information
• Common information: File name/Drive name
3013
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
[PARAMETER ERROR]
In a multiple CPU system, the multiple CPU auto
refresh setting is any of the following.
• The device specified is other than the one that
may be specified.
• The number of send points is an odd number.
• The total number of send points is greater than
the maximum number of refresh points.
• The setting of the refresh range crosses over the
boundary between the internal user device and
the extended data register (D) or extended link
register (W).
• No device is set in the host CPU send range.
■Collateral information
• Common information: File name/Drive name
• Individual information: Parameter number
■Diagnostic Timing
• At power-on/At reset/STOP→RUN/At writing to
programmable controller
Corrective Action
The number of CPU modules in the multiple CPU
system must be the same as the value derived as
follows: (the number of CPU modules set in the
multiple CPU setting) - (the number of PLC
(empty) slots set in the I/O assignment).
Match the multiple CPU setting or control CPU
setting in the PLC parameter with that of the
reference CPU (CPU No.1) settings.
Check the following for the refresh setting in the
Multiple CPU settings dialog box, and correct it.
• When specifying the bit device, specify a
multiple of 16 for the refresh starting device.
• Specify the device that may be specified for the
refresh device.
• Set the number of send points to an even
number.
Check the following for the refresh setting in the
Multiple CPU settings dialog box, and correct it.
• The total number of transmission points is
within the maximum number of refresh points.
Check the following in the refresh setting in the
Multiple CPU settings dialog box, and correct the
setting.
• Specify the device that may be specified for the
refresh device.
• Set the number of send points to an even
number.
• Set the total number of send points within the
range of the maximum number of refresh
points.
• Set the refresh range so that it does not cross
over the boundary between the internal user
device and the extended data register (D) or
extended link register (W).
• For the send range of the host CPU, refresh
target device must be specified. If a send range
is not necessary, delete the applicable send
range.
LED Status Corresponding
CPU Status CPU
*8
Qn(H)
QnPH
*8
Q00/Q01
*8
Qn(H)
QnU
*8
Qn(H)
QnPH
RUN:
Off
ERR.:
Flicker
CPU Status:
Stop
*8
Q00/Q01
*18
QnU
12-45
1
2
3
12
6
6
7
8