Lpc Super I/O (Sio)/Lpc Slot; Serial Port, Irda; System Management Controller (Smc)/Keyboard Controller (Kbc); Table 13. Usb2.0 Ports - Intel 6 Series User Manual

Table 13. USB2.0 Ports

OC0#
OC1#
OC2#
OC3#
OC4#
OC5#
OC6#
OC7#
3.2.9

LPC Super I/O (SIO)/LPC Slot

A SMSC SIO1007* serves as the SIO on the development board and is located at
U9A1. Shunting the jumper at J8C3 to the 2-3 positions can disable the SIO by
holding it in reset. This allows other SIO solutions to be tested in the LPC slot at J8F2.
A sideband header is provided at J9G2 for this purpose. This sideband header also has
signals for LPC power management.
3.2.10

Serial Port, IrDA

The SMSC SIO incorporates a serial port, and IrDA (Infrared), as well as general-
purpose IOs (GPIO). The Serial Port connector is provided at J1A2. The IrDA
transceiver on the development board supports SIR (slow IR), FIR (Fast IR) and CIR
(Consumer IR). The option to select between these is supported through software and
GPIO pin (IR_MODE) on the SIO.
3.2.11 System Management Controller (SMC)/Keyboard
Controller (KBC)
A Renesas H8S/2117* (U9G4) serves as both SMC and KBC for the development
board. The SMC/KBC controller supports two PS/2 ports, battery monitoring and
charging, wake/runtime SCI events, CPU thermal monitoring/fan control, GMCH
thermal throttling support, LPC docking support and power sequencing control. Also,
the PECI, which was earlier supported from PCH to CPU is now supported directly from
EC, since the EC now has built-in PECI.
The two PS/2 ports on the board are for legacy keyboard and mouse. The keyboard
plugs into the bottom jack and the mouse plugs into the top jack at J1A1. Scan matrix
keyboards can be supported via a connector at J9E2.
There is an LPC slot (J8F2) and LPC Sideband connector (J9G2) on the board to
connect external EC for validation purposes. On-board EC has to be disabled by
shorting pin 1 and 2 of connector J9F2 and external EC has to handle board power
sequencing and thermal management.
2 nd Generation Intel ® Core™ Processor with Intel
User Guide
40
0 and 1
2 and 3
4 and 5
6 and 7
8 and 9
10 and 11
12 and 13
GPIO
® 6 Series Chipset Development Kit
Development Kit Features
March 2011
Document Number: 325208-001