Rambus Drcg* Impedance Matching Circuit; Figure 25. Rambus Drcg* Impedance Matching Network; Table 7. Rambus Drcg* Impedance Matching Network Values - Intel Pentium 4 Design Manual

Platform Clock Routing Guidelines
4.3.4

Rambus DRCG* Impedance Matching Circuit

The external DRCG impedance matching circuit is shown in Figure 25.

Figure 25. Rambus DRCG* Impedance Matching Network

Table 7. Rambus DRCG* Impedance Matching Network Values

Component
C
MID1
FBead
CD2
CBulk
NOTES:
1. Note the removal of the original EMI capacitors between the junctions of RS, RP and ground. These
capacitors had minimal impact on EMI and increased DRCG output jitter by approximately 2X.
2. The intent of component CF is to decouple CLK and CLKB outputs to each other, but data shows this
actually increases device jitter. CF should not be stuffed at this time.
3. The ferrite bead and 10 µF bulk capacitor combination improves jitter and helps to keep the clock noise
away from the rest of the system.
4. 0.1 µF capacitors are better than 0.01 µF or 0.001 µF capacitors for DRCG decoupling.
5. Cmid at 0.1 µF has improved jitter versus Cmid at 100 pF. However, this will increase the latency
coming out of a stop clock or tri-state mode.
6. RS, RP, RT were modified to improve channel signal integrity through increasing CTM/CTMN swing.
54
C
D
V
V
O
IR
DD DD
V
P
DD
C
D
DRCG
C
D
V
C
DD
V
IPD
DD
V
O
DD
C
D
Nominal Value
C 0.1 µF
D
R
S
R
P
, C 0.1 µF
MID2
R
T
C 4–15 pF
F
50 Ω @ 100 MHz
0.1 µF
® ®
Intel Pentium 4 Processor / Intel
To 3.3V DRCG
Supply
Connection
CD2
CD2
C
D
Z
CH
R R
S P
C
MID
C
F
R
R
Z
P
S CH
C
D
Decoupling capacitors to GND
39 Ω
Series termination resistor
51 Ω Parallel termination resistor
Virtual GND caps
27 Ω
End of channel termination
Do Not Stuff, leave pads for future use
Ferrite bead
Additional 3.3 V decoupling caps
10 µF Bulk capacitor on device side of ferrite bead
®
850 Chipset Family Platform Design Guide
3.3v
FBead
CBulk
R
T
C
MID 2
R
T
DRCG_Imp_Match
Notes
R