Cpu Control Register; Isa Local Resource Bus; W83C553 Pib Registers; Primary And Secondary Eide Ports - Motorola MTX Series Programmer's Reference Manual

CPU Control Register

The CPU Control Register is accessed via the RD[32:39] data lines of the
upper Falcon device. This 8-bit register is defined as follows:
Register
Bit 0
Field
Operation R
Reset 0
GETPCI Get PCI Bus. This bit is logically ORed with Raven's PCI bus
request signal. It can be used to obtain the PCI bus for the Processor.
LEMODE Little-endian Mode. This bit must be set in conjunction with
the LEND bit in the Raven for little-endian mode.
P0/1_TBEN Processor 0/1 Time Base Enable. When this bit is cleared,
the TBEN pin of Processor 0/1 will be driven low.

ISA Local Resource Bus

W83C553 PIB Registers

The PIB contains ISA Bridge I/O registers for various functions. These
registers are accessible from the PCI bus. Refer to the W83C553 Data
Book for details.

Primary and Secondary EIDE Ports

The PIB also contains the EIDE controller. Refer to the 83C553 Data Book
for details.
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CPU Control Register - $FEF88300
1 2 3
R R/W R/W
0 1 1
ISA Local Resource Bus
4 5
R R R
X X X
1
6 7
R
X
1-23