Clk Frequency Register - Motorola MVME5100 Programmer's Reference Manual

System Memory Controller (SMC)

CLK Frequency Register

Address
Bit
3
Name
CLK FREQUENCY
Operation
Reset
CLK FREQUENCY
3-44
READ/WRITE READ ZERO
64 P
These bits should be programmed with the hexadecimal
value of the operating CLOCK frequency in MHz (i.e. $42
for 66 MHz). When these bits are programmed this way,
the chip's prescale counter produces a 1 MHz
(approximate) output. The output of the chip prescale
counter is used by the refresher/scrubber and the 32-bit
counter. After power-up, this register is initialized to $64
(for 100 MHz). The formula is:
Counter_Output_Frequency = (Clock
Frequency)/CLK_FREQUENCY
For example, if the Clock Frequency is 100 MHz and
CLK_FREQUENCY is $64, then the counter output
frequency is 100 MHz/100 = 1 MHz.
When the CLK pin is operating slower than 100MHz,
software should program CLK_FREQUENCY to be at
least as slow as the CLK pin's frequency as soon as
possible after power-up reset so that SDRAM refresh does
not get behind. It is okay for the software then to take
some time to "up" CLK_FREQUENCY to the correct
value. Refresh will get behind only when the actual CLK
pin's frequency is lower than the value programmed into
CLK_FREQUENCY.
por por is set by the occurrence of power up reset. It is cleared
by writing a one to it. Writing a 0 to it has no effect.
$FEF80020
READ ZERO
X X
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