Table 3-5. Powerpc 60X Bus To Dram Access Timing Using 60Ns Page - Motorola MVME2301 Installation And Use Manual

Table 3-5. PowerPC 60x Bus to DRAM Access Timing using 60ns Page

Access Type
4-Beat Read after Idle
(Quad-word aligned)
4-Beat Read after Idle
(Quad-word misaligned)
4-Beat Read after 4-Beat Read
(Quad-word aligned)
4-Beat Read after 4-Beat Read
(misaligned)
4-Beat Write after Idle
4-Beat Write after 4-Beat
Write (Quad-word aligned)
1-Beat Read after Idle
1-Beat Read after 1-Beat Read
1-Beat Write after Idle
1-Beat Write after 1-Beat
Write
Notes 1. These numbers assume that the PowerPC 60x bus
Devices
Clock Periods Required for:
1st Beat 2nd Beat
9 1
9 3
1
7/3 1
1
6/2 3
4 1
1
7/3 1
9 -
1
8/6 -
-
4
1
-
12/10
master is doing address pipelining with TS* occurring
at the minimum time after AACK* is asserted. Also the
two numbers shown in the 1st beat column are for page
miss/page hit.
2. In some cases, the numbers shown are averages and
specific instances may be longer or shorter.
Functional Description
3rd Beat 4th Beat
2 1
1 1
2 1
1 1
1 1
1 1
- -
- -
- -
- -
3
Total
Clocks
13
14
11/7
11/7
7
10/6
9
8/6
4
12/10
3-9