Vendor Identification Register; Processor Init Register - Motorola MVME5100 Programmer's Reference Manual
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Also See for MVME5100:
- Programmer's reference manual (320 pages) ,
- Manual (127 pages) ,
- Installation & use manual (107 pages)
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Hawk PCI Host Bridge & Multi-Processor Interrupt Controller
Vendor Identification Register
2
Offset
Bit
3
1
Name
Operation
Reset
Processor Init Register
Offset
Bit
3
1
Name
Operation
Reset
2-114
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
VENDOR IDENTIFICATION
R
$00
There are two fields in the Vendor Identification Register which are not
defined for the MPIC implementation but are defined in the MPIC
specification. They are the vendor identification and device ID fields.
STP
STEPPING.The stepping or silicon revision number of
Hawk's MPIC.
3
2
2
2
2
2
2
2
2
0
9
8
7
6
5
4
3
2
R
$00
P1
PROCESSOR 1. Writing a 1 to P1 will assert the Soft
Reset input of processor 1. Writing a 0 to it will negate the
SRESET signal.
P0
PROCESSOR 0. Writing a 1 to P0 will assert the Soft
Reset input of processor 0. Writing a 0 to it will negate the
SRESET signal.
The Soft Reset input to the 604 is negative edge-sensitive.
$01080
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
STP
R
$00
$00
$01090
2
2
1
1
1
1
1
1
1
1
0
9
8
7
6
5
4
3
PROCESSOR INIT
R
$00
$00
Computer Group Literature Center Web Site
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
R
$00
1
1
1
2
1
0 9 8 7 6 5 4 3 2 1 0
R
R
$00
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